Measured By The Line

(It's Exotic Code Day, jut for all you underrepresented hardware fans)

Adam worked for one of the very few remaining managers who actually measure performance and productivity by the number of lines of code produced. It was pretty easy for the manager to get away with such a management style as his department was a small, low-profile group named the Special Hardware Projects group, and was hidden away under layers of other management inside of a behemoth software/hardware organization (we'll call them "Moon Microsystems").

Since the group had been lagging a bit behind on some of its projects, the manager decided that the best possible way to improve delivery time was to switch from VHDL (a "slower" to develop language) to a Verilog (a "faster" to develop language). The lead programmer on the team was behind his boss' change all the way; well, that is, until he realized how embarrassingly compact the code was. Consider, for example, the following logic for CPU model identification:

module idreg(sout,sel, capture, sen, ti, tck, logic_0, logic_1);
output sout ;
input  sel, capture, sen, ti, tck, logic_0, logic_1 ;

       // comments removed

       wire [31:0] din = 32'h0000202F;

       wire cap = sel & capture;
       wire te  = sel & sen;

       wire [31:0] out ;
       wire sout = out[0] ;
       Mflipflop_sh_32 ff1(out, din, te, {ti,out[31:1]}, ~cap, tck) ;       
endmodule

Knowing that his boss would have a hissy-fit when he saw how few lines of code were produced, the lead programmer starting encouraging the other programmers to start making "size optimizations" across the system. For this same CPU model identification, they took the VCC and GND pins from the chip and routed them down to the 7/8 level of hierarchy to to this particular module, renaming them "logic_0" and "logic_1". Then they changed the module's code:

module idreg(sout,sel, capture, sen, ti, tck, logic_0, logic_1);
output sout ;
input  sel, capture, sen, ti, tck, logic_0, logic_1 ;

       // comments removed

       re [31:0] din =   {logic_0,
                          logic_0,
                          logic_1,
                          logic_1,

                          logic_0,
                          logic_0,
                          logic_0,
                          logic_0,
                          logic_0,
                          logic_0,
                          logic_0,
                          logic_1,

                          logic_0,
                          logic_1,
                          logic_1,
                          logic_0,
                          logic_1,
                          logic_1,
                          logic_0,
                          logic_1,

                          logic_0,
                          logic_0,
                          logic_0,

                          logic_0,
                          logic_0,
                          logic_1,
                          logic_1,
                          logic_0,
                          logic_1,
                          logic_1,
                          logic_0,

                          logic_1};

       wire cap = sel & capture;
       wire te  = sel & sen;

       wire [31:0] out ;
       wire sout = out[0] ;
       Mflipflop_sh_32 ff1(out, din, te, {ti,out[31:1]}, ~cap, tck) ;       
endmodule

As you might imagine, all this "size optimization" ended up taking a lot more time, resulted in quite a bit more bugs, and caused the team to miss the project deadline by months. But, there was a whole lot more lines of code. And when you think about it, that's all that really matters.

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